7e4f2be406
This allows performing synthesis of VHDL using ghdl with yosys. Signed-off-by: Nico Sonack <nsonack@herrhotzenplotz.de> PR: 274243
33 lines
771 B
Makefile
33 lines
771 B
Makefile
PORTNAME= yosys-ghdl-plugin
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PORTVERSION= g20230930
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CATEGORIES= cad
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MAINTAINER= nsonack@outlook.com
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COMMENT= GHDL synthesis plugin for yosys
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WWW= https://github.com/ghdl/ghdl-yosys-plugin
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LICENSE= GPLv3
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BUILD_DEPENDS= ghdl>0:cad/ghdl \
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yosys>0:cad/yosys
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RUN_DEPENDS= yosys>0:cad/yosys
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LIB_DEPENDS= libffi.so:devel/libffi \
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libghdl-3_0_0.so:cad/ghdl \
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libtcmalloc.so:devel/google-perftools
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USES= gmake readline tcl
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USE_GITHUB= yes
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GH_ACCOUNT= ghdl
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GH_PROJECT= ghdl-yosys-plugin
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GH_TAGNAME= d44a7bccdaa458ab3ec0ce83459410604bee6c60
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MAKE_ENV+= GHDL=${LOCALBASE}/bin/ghdl \
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YOSYS_CONFIG=${LOCALBASE}/bin/yosys-config
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PLIST_FILES= share/yosys/plugins/ghdl.so
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post-install:
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${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/ghdl.so
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.include <bsd.port.mk>
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