Convert to test framework

Approved by: portmgr (blanket)
2017-10-12 08:09:44 +00:00
parent 3b482ca6aa
commit 02ff99a147
1 changed files with 0 additions and 3 deletions
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -24,7 +24,4 @@ post-install:
 	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
 	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so

-regression-test: build
-	make test -C ${WRKSRC}
-
 .include <bsd.port.mk>