cad/apio: New port: Open source ecosystem for open FPGA boards
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@@ -6,6 +6,7 @@
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SUBDIR += adms
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SUBDIR += alliance
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SUBDIR += antimony
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SUBDIR += apio
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SUBDIR += appcsxcad
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SUBDIR += archimedes
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SUBDIR += astk-client
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@@ -0,0 +1,28 @@
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PORTNAME= apio
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DISTVERSION= 0.8.4
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CATEGORIES= cad python
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MASTER_SITES= PYPI
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= Open source ecosystem for open FPGA boards
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WWW= https://github.com/FPGAwars/apio/wiki
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LICENSE= GPLv2
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LICENSE_FILE= ${WRKSRC}/LICENSE
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PY_DEPENDS= ${PYTHON_PKGNAMEPREFIX}click>=8.1.3:devel/py-click@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}colorama>0:devel/py-colorama@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}pyserial>=3.5:comms/py-pyserial@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}requests>=2.28.2:www/py-requests@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}semantic-version>=2.9.0:devel/py-semantic-version@${PY_FLAVOR}
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BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}flit-core>=2:devel/py-flit-core@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}wheel>=0.35.0<1:devel/py-wheel@${PY_FLAVOR} \
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${PY_DEPENDS}
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RUN_DEPENDS= ${PY_DEPENDS}
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USES= python scons
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USE_PYTHON= pep517 autoplist
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NO_ARCH= yes
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.include <bsd.port.mk>
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@@ -0,0 +1,3 @@
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TIMESTAMP = 1704526040
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SHA256 (apio-0.8.4.tar.gz) = baa8edbdf933ff098178418214b19dfce0cad233ecbe5fc73b896bb7434b5d8f
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SIZE (apio-0.8.4.tar.gz) = 1150556
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@@ -0,0 +1,22 @@
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--- pyproject.toml.orig 2024-01-06 07:32:13 UTC
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+++ pyproject.toml
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@@ -16,13 +16,13 @@ requires = [
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description-file = "README.md"
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requires-python = ">=3.7"
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requires = [
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- 'click==8.1.3',
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- 'semantic_version==2.9.0',
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- 'requests==2.28.2',
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- 'colorama==0.4.6',
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- 'pyserial==3.5',
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+ 'click>=8.1.3',
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+ 'semantic_version>=2.9.0',
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+ 'requests>=2.28.2',
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+ 'colorama>0',
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+ 'pyserial>=3.5',
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'wheel>=0.35.0,<1',
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- 'scons==4.2.0'
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+ 'scons>=4.2.0'
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]
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[tool.flit.sdist]
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@@ -0,0 +1,3 @@
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Apio is a multiplatform toolbox with static pre-built packages to verify,
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synthesize, simulate and upload your verilog designs into the supported FPGA
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boards.
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