cad/apio: New port: Open source ecosystem for open FPGA boards

This commit is contained in:
Yuri Victorovich
2024-01-06 00:03:02 -08:00
parent e7b86e162f
commit 88ab25bebe
5 changed files with 57 additions and 0 deletions
+1
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@@ -6,6 +6,7 @@
SUBDIR += adms
SUBDIR += alliance
SUBDIR += antimony
SUBDIR += apio
SUBDIR += appcsxcad
SUBDIR += archimedes
SUBDIR += astk-client
+28
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@@ -0,0 +1,28 @@
PORTNAME= apio
DISTVERSION= 0.8.4
CATEGORIES= cad python
MASTER_SITES= PYPI
MAINTAINER= yuri@FreeBSD.org
COMMENT= Open source ecosystem for open FPGA boards
WWW= https://github.com/FPGAwars/apio/wiki
LICENSE= GPLv2
LICENSE_FILE= ${WRKSRC}/LICENSE
PY_DEPENDS= ${PYTHON_PKGNAMEPREFIX}click>=8.1.3:devel/py-click@${PY_FLAVOR} \
${PYTHON_PKGNAMEPREFIX}colorama>0:devel/py-colorama@${PY_FLAVOR} \
${PYTHON_PKGNAMEPREFIX}pyserial>=3.5:comms/py-pyserial@${PY_FLAVOR} \
${PYTHON_PKGNAMEPREFIX}requests>=2.28.2:www/py-requests@${PY_FLAVOR} \
${PYTHON_PKGNAMEPREFIX}semantic-version>=2.9.0:devel/py-semantic-version@${PY_FLAVOR}
BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}flit-core>=2:devel/py-flit-core@${PY_FLAVOR} \
${PYTHON_PKGNAMEPREFIX}wheel>=0.35.0<1:devel/py-wheel@${PY_FLAVOR} \
${PY_DEPENDS}
RUN_DEPENDS= ${PY_DEPENDS}
USES= python scons
USE_PYTHON= pep517 autoplist
NO_ARCH= yes
.include <bsd.port.mk>
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@@ -0,0 +1,3 @@
TIMESTAMP = 1704526040
SHA256 (apio-0.8.4.tar.gz) = baa8edbdf933ff098178418214b19dfce0cad233ecbe5fc73b896bb7434b5d8f
SIZE (apio-0.8.4.tar.gz) = 1150556
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@@ -0,0 +1,22 @@
--- pyproject.toml.orig 2024-01-06 07:32:13 UTC
+++ pyproject.toml
@@ -16,13 +16,13 @@ requires = [
description-file = "README.md"
requires-python = ">=3.7"
requires = [
- 'click==8.1.3',
- 'semantic_version==2.9.0',
- 'requests==2.28.2',
- 'colorama==0.4.6',
- 'pyserial==3.5',
+ 'click>=8.1.3',
+ 'semantic_version>=2.9.0',
+ 'requests>=2.28.2',
+ 'colorama>0',
+ 'pyserial>=3.5',
'wheel>=0.35.0,<1',
- 'scons==4.2.0'
+ 'scons>=4.2.0'
]
[tool.flit.sdist]
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@@ -0,0 +1,3 @@
Apio is a multiplatform toolbox with static pre-built packages to verify,
synthesize, simulate and upload your verilog designs into the supported FPGA
boards.